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🎨 support cds as input for all simulators #310
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clang-tidy made some suggestions
include/fiction/algorithms/simulation/sidb/can_positive_charges_occur.hpp
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Codecov ReportAll modified lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #310 +/- ##
=======================================
Coverage 96.00% 96.01%
=======================================
Files 100 100
Lines 9916 9935 +19
=======================================
+ Hits 9520 9539 +19
Misses 396 396
☔ View full report in Codecov by Sentry. |
TEMPLATE_TEST_CASE( | ||
"QuickExact simulation of a 3 DB Wire", "[quickexact]", | ||
(cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>), | ||
(charge_distribution_surface<cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>>)) |
Check warning
Code scanning / CodeQL
Poorly documented large function Warning test
TEMPLATE_TEST_CASE( | ||
"QuickSim simulation of an layout comprising of 13 SiDBs", "[quicksim]", | ||
(cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>), | ||
(charge_distribution_surface<cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>>)) |
Check warning
Code scanning / CodeQL
Poorly documented large function Warning test
TEMPLATE_TEST_CASE( | ||
"ExGS simulation of a Y-shape SiDB OR gate with input 01", "[exhaustive-ground-state-simulation]", | ||
(cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>), | ||
(charge_distribution_surface<cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>>)) |
Check warning
Code scanning / CodeQL
Poorly documented large function Warning test
TEMPLATE_TEST_CASE( | ||
"QuickExact simulation of a Y-shape SiDB OR gate with input 01", "[quickexact]", | ||
(cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>), | ||
(charge_distribution_surface<cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>>)) |
Check warning
Code scanning / CodeQL
Poorly documented large function Warning test
TEMPLATE_TEST_CASE( | ||
"QuickSim simulation of an SiDB layout comprising of 10 SiDBs with varying thread counts", "[quicksim]", | ||
(cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>), | ||
(charge_distribution_surface<cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>>)) |
Check warning
Code scanning / CodeQL
Poorly documented large function Warning test
TEMPLATE_TEST_CASE( | ||
"QuickSim simulation of a Y-shape SiDB OR gate with input 01", "[ExGS]", | ||
(cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>), | ||
(charge_distribution_surface<cell_level_layout<sidb_technology, clocked_layout<cartesian_layout<siqad::coord_t>>>>)) |
Check warning
Code scanning / CodeQL
Poorly documented large function Warning test
Lot's of false positives for some reason by the |
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clang-tidy made some suggestions
Description
This PR adds
charge_distribution_surface
(cds) as a possible input for all simulators.Checklist: